library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;


entity ALU is 
port(x, y : in std_logic_vector(31 downto 0);
	add_sub : in std_logic;
	logic_func : in std_logic_vector(1 downto 0);
	func : in std_logic_vector(1 downto 0);
	output : out std_logic_vector(31 downto 0);
	overflow : out std_logic;
	zero : out std_logic);
end ALU;

architecture calc of ALU is
	signal logic_unit_output, add_subtract_output: std_logic_vector(31 downto 0);

begin
	outputmux: process(func, add_subtract_output, logic_unit_output, y)
		begin
			case func is
				when "00" =>
					output <= y;
				when "01" =>
					output <= "0000000000000000000000000000000" & add_subtract_output(31);
				when "10" =>
					output <= add_subtract_output;
				when "11" =>
					output <= logic_unit_output;
				when others =>
					null;
			end case;
	end process outputmux;

	logicunit: process(logic_func, x, y)
		begin
			case logic_func is 
				when "00" =>
					logic_unit_output <= x and y;
				when "01" =>
					logic_unit_output <= x or y;
				when "10" =>
					logic_unit_output <= x xor y;
				when "11" =>
					logic_unit_output <= x nor y;
				when others =>
					logic_unit_output <= (others => '0');
			end case;
	end process logicunit;
	
	adder_subtract: process(y, x, add_sub)
		begin
			if add_sub = '0' then
				add_subtract_output <= x + y;
			elsif add_sub = '1' then
				add_subtract_output <= x - y;
			else
				null;
			end if;
	end process adder_subtract;

	zeroreg: process(add_subtract_output)
		begin
			if (unsigned(add_subtract_output) = 0) then
				zero <= '1';
			else
				zero <= '0';
			end if;
	end process zeroreg;
		
	overflowreg: process(x, y, add_subtract_output, add_sub)
		begin
			case add_sub is
				when '0' =>
					if (x(31) = '0' and y(31) = '0' and add_subtract_output(31) = '1') then
						overflow <= '1';
					elsif (x(31) = '1' and y(31) = '1' and add_subtract_output(31) = '0') then
						overflow <= '1';
					else
						overflow <= '0';
					end if;
				when '1' =>
					if (x(31) = '1' and y(31) = '0' and add_subtract_output(31) = '0') then
						overflow <= '1';
					elsif (x(31) = '0' and y(31) = '1' and add_subtract_output(31) = '1') then
						overflow <= '1';
					else
						overflow <='0';
					end if;
				when others =>
					null;
			end case;
	end process overflowreg;
						
end;