library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity cpu is
port(reset : in std_logic;
 clk : in std_logic;
 rs_out, rt_out : out std_logic_vector(3 downto 0); -- output ports from register file
 pc_out : out std_logic_vector(3 downto 0); -- pc reg
 overflow, zero : out std_logic);
end cpu;

architecture cpu5 of cpu is
--components
component next_address
port(rt, rs : in std_logic_vector(31 downto 0);
	pc : in std_logic_vector(31 downto 0);
	target_address : in std_logic_vector(25 downto 0);
	branch_type : in std_logic_vector(1 downto 0);
	pc_sel : in std_logic_vector(1 downto 0);
	next_pc : out std_logic_vector(31 downto 0));
end component;

component pc_icache --ADD AN OUTPUT FOR OPCODEROUTE
port(

	clk, reset, reg_dst : in std_logic;
	nextaddressout_pcin : in std_logic_vector(31 downto 0);
	instruction : out std_logic_vector (31 downto 0);
	pcout : out std_logic_vector(31 downto 0);
	instruction_target_address : out std_logic_vector(25 downto 0);
	output_address_regfile : out std_logic_vector(4 downto 0);
	rs_out, rt_out, rd_out : out std_logic_vector(4 downto 0);
	immediate_out : out std_logic_vector(15 downto 0));
end component;

component regfile
port( din : in std_logic_vector(31 downto 0);
		reset : in std_logic;
		clk : in std_logic;
		write : in std_logic;
		read_a : in std_logic_vector(4 downto 0);
		read_b : in std_logic_vector(4 downto 0);
		write_address : in std_logic_vector(4 downto 0);
		out_a : out std_logic_vector(31 downto 0);
		out_b : out std_logic_vector(31 downto 0));
end component;

component signextension_mux
port(
	func : in std_logic_vector(1 downto 0);
	immediate : in std_logic_vector(15 downto 0);
	out_b_input : in std_logic_vector(31 downto 0);
	alu_src : in std_logic;
	muxout_aluin : out std_logic_vector(31 downto 0));
end component;

component ALU
port(x, y : in std_logic_vector(31 downto 0);
	add_sub : in std_logic;
	logic_func : in std_logic_vector(1 downto 0);
	func : in std_logic_vector(1 downto 0);
	output : out std_logic_vector(31 downto 0);
	overflow : out std_logic;
	zero : out std_logic);
end component;

component datacache
port(
	clk, reset, data_write, reg_in_src : in std_logic;
	mux_d_output : out std_logic_vector(31 downto 0);
	d_cache_in : in std_logic_vector(31 downto 0);
	aluout_dcachein : in std_logic_vector(31 downto 0));
end component;

component opcoderoute
port(
	icacheout_combin : in std_logic_vector(31 downto 0);
	reg_write, reg_dst, reg_in_src, alu_src, add_sub, data_write: out std_logic;
	logic_func, alu_func, sign_extend_func, branch_type, pc_sel: out std_logic_vector(1 downto 0));
end component;

--signal

signal insig_pc_sel, insig_branch_type, insig_func_sign, insig_func_alu, insig_logic_func : std_logic_vector(1 downto 0);
signal insig_reset, insig_clk, insig_reg_dst, insig_reg_write, insig_alu_src, insig_add_sub, insig_data_write, insig_reg_in_src : std_logic;
signal insig_ta : std_logic_vector(25 downto 0);

signal iout_opcoderoute, pcout_nain, naout_pcin, d_in_sig, out_a_sig, out_b_sig, muxout_aluyin, alu_out: std_logic_vector(31 downto 0);

signal rd_rt, rs_read_a, rt_read_b, rd_address: std_logic_vector(4 downto 0);

signal immediate_extend: std_logic_vector(15 downto 0);

--signal iout_opcoderoute, pcout_nain,naout_pcin,d_in_sig,out_a_sig,out_b_sig,muxout_aluyin,alu_out : std_logic_vector(31 downto 0);
--signal rd_rt, rs_read_a, rt_read_b, rd_address : std_logic_vector(4 downto 0);
--signal immediate_extend: std_logic_vector(15 downto 0);


for U1: next_address use entity WORK.next_address(next_add_arch);
for U2: pc_icache use entity WORK.pc_icache(pc_i_cache);
for U3: regfile use entity WORK.regfile(unti);
for U4: signextension_mux use entity WORK.signextension_mux(sign_extension);
for U5: ALU use entity WORK.ALU(calc);
for U6: datacache use entity WORK.datacache(data_c_arch);
for U7: opcoderoute use entity WORK.opcoderoute(opcoderoute_arch);

begin

rs_out <= out_a_sig(3 downto 0);
rt_out <= out_b_sig(3 downto 0);
pc_out <= pcout_nain(3 downto 0);


U1: next_address port map (rt => out_b_sig, rs=> out_a_sig, pc=> pcout_nain, target_address=> insig_ta, branch_type=> insig_branch_type, pc_sel=> insig_pc_sel, next_pc=> naout_pcin);
U2: pc_icache port map (clk => clk, reset => reset, reg_dst => insig_reg_dst, nextaddressout_pcin => naout_pcin, instruction => iout_opcoderoute, pcout=>pcout_nain, output_address_regfile => rd_rt, rs_out => rs_read_a, rt_out => rt_read_b, rd_out => rd_address, immediate_out => immediate_extend, instruction_target_address => insig_ta);
U3: regfile port map (din => d_in_sig, reset => reset, clk => clk, write => insig_reg_write, read_a => rs_read_a, read_b => rt_read_b, write_address => rd_rt, out_a => out_a_sig, out_b => out_b_sig);
U4: signextension_mux port map (func => insig_func_sign, immediate => immediate_extend, out_b_input => out_b_sig, alu_src => insig_alu_src, muxout_aluin => muxout_aluyin);
U5: ALU port map (x => out_a_sig, y => muxout_aluyin, add_sub => insig_add_sub, logic_func => insig_logic_func, func => insig_func_alu, output => alu_out, overflow => overflow, zero => zero);
U6: datacache port map (clk => clk, reset => reset, data_write => insig_data_write, reg_in_src => insig_reg_in_src, mux_d_output => d_in_sig, d_cache_in => out_b_sig, aluout_dcachein => alu_out);
U7: opcoderoute port map (icacheout_combin => iout_opcoderoute, reg_write => insig_reg_write, reg_dst => insig_reg_dst, reg_in_src => insig_reg_in_src, alu_src => insig_alu_src, add_sub => insig_add_sub, data_write => insig_data_write, logic_func => insig_logic_func, alu_func => insig_func_alu, sign_extend_func => insig_func_sign, branch_type => insig_branch_type, pc_sel => insig_pc_sel);
end cpu5;