library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity datacache is
port(
	clk, reset, data_write, reg_in_src : in std_logic;
	mux_d_output : out std_logic_vector(31 downto 0);
	d_cache_in : in std_logic_vector(31 downto 0);
	aluout_dcachein : in std_logic_vector(31 downto 0));
end datacache;

architecture data_c_arch of datacache is
	type dcache is array (31 downto 0) of std_logic_vector(31 downto 0);
	
	signal d_cache : dcache := (others => (others => '0'));
	signal d_cache_address : std_logic_vector(4 downto 0);
	signal d_cache_out : std_logic_vector(31 downto 0);
begin

d_cache_address <= aluout_dcachein(4 downto 0);

data_cache:process(clk, reset,d_cache_in, d_cache_address)
begin
		if (reset = '1') then
			d_cache(0) <= (others => '0');
			d_cache(1) <= (others => '0');
			d_cache(2) <= (others => '0');
			d_cache(3) <= (others => '0');
			d_cache(4) <= (others => '0');
			d_cache(5) <= (others => '0');
			d_cache(6) <= (others => '0');
			d_cache(7) <= (others => '0');
			d_cache(8) <= (others => '0');
			d_cache(9) <= (others => '0');
			d_cache(10) <= (others => '0');
			d_cache(11) <= (others => '0');
			d_cache(12) <= (others => '0');
			d_cache(13) <= (others => '0');
			d_cache(14) <= (others => '0');
			d_cache(15) <= (others => '0');
			d_cache(16) <= (others => '0');
			d_cache(17) <= (others => '0');
			d_cache(18) <= (others => '0');
			d_cache(19) <= (others => '0');
			d_cache(20) <= (others => '0');
			d_cache(21) <= (others => '0');
			d_cache(22) <= (others => '0');
			d_cache(23) <= (others => '0');
			d_cache(24) <= (others => '0');
			d_cache(25) <= (others => '0');
			d_cache(26) <= (others => '0');
			d_cache(27) <= (others => '0');
			d_cache(28) <= (others => '0');
			d_cache(29) <= (others => '0');
			d_cache(30) <= (others => '0');
			d_cache(31) <= (others => '0');
		elsif (clk'event and clk ='1' and data_write = '1') then
			d_cache(conv_integer(d_cache_address)) <= d_cache_in;
		end if;	
end process data_cache;

d_cache_mux:process(reg_in_src,d_cache_address,aluout_dcachein,d_cache)
begin
	case reg_in_src is
		when '0' =>
		mux_d_output <= d_cache(conv_integer(d_cache_address));
		when '1' =>
		mux_d_output <= aluout_dcachein;
		when others =>
	end case;
end process d_cache_mux;

end data_c_arch;