library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
entity next_address is
port(rt, rs : in std_logic_vector(31 downto 0);
 -- two register inputs
	pc : in std_logic_vector(31 downto 0);
	target_address : in std_logic_vector(25 downto 0);
	branch_type : in std_logic_vector(1 downto 0);
	pc_sel : in std_logic_vector(1 downto 0);
	next_pc : out std_logic_vector(31 downto 0));
end next_address ;

architecture next_add_arch of next_address is
	signal branch_offset: std_logic_vector(31 downto 0);
begin
	
inpuediting:process(pc, target_address)
begin
	
	if (target_address(15) = '0') then --sign extension branch_offset
		branch_offset(31 downto 16) <= (others => '0');
		branch_offset(15 downto 0) <= target_address(15 downto 0);
	else --sign extension branch_offset
		branch_offset(31 downto 16) <= (others => '1');
		branch_offset(15 downto 0) <= target_address(15 downto 0);
	end if;
end process inpuediting;

--pc_inc <= pc + "00000000000000000000000000000001";

PCMUX:process(pc_sel, branch_type, rs, rt, branch_offset, target_address, pc)
begin
	case pc_sel is
		when "00" =>
			case branch_type is
				when "01" => --beq
					if (rs = rt) then
						next_pc <= pc + "00000000000000000000000000000001" + branch_offset(31 downto 0);
					end if;
				when "10" => --bne
					if (rs /= rt) then
						next_pc	<= pc + "00000000000000000000000000000001" + branch_offset(31 downto 0);
					end if;
				when "11" => --bltz
					if (rs(31) = '1') then 
						next_pc <= pc + "00000000000000000000000000000001" + branch_offset(31 downto 0);
					end if;
				when "00" => --pc increment
					next_pc <= pc + "00000000000000000000000000000001";
				when others =>
			end case;
		when "01" => --jump address
			next_pc <= "000000" & target_address;
		when "10" => --jump rs
			next_pc <= rs;
		when others => --next_pc = pc
			next_pc <= pc;
	end case;
end process PCMUX;
			
end next_add_arch;