--lab2draft1
-- 32 x 32 register file
-- two read ports, one write port with write enable
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity regfile is
port( din : in std_logic_vector(31 downto 0);
		reset : in std_logic;
		clk : in std_logic;
		write : in std_logic;
		read_a : in std_logic_vector(4 downto 0);
		read_b : in std_logic_vector(4 downto 0);
		write_address : in std_logic_vector(4 downto 0);
		out_a : out std_logic_vector(31 downto 0);
		out_b : out std_logic_vector(31 downto 0));
end regfile ;

architecture unti of regfile is

	type registerfile is array (31 downto 0) of std_logic_vector(31 downto 0);-- := (others => (others => '0'));

	signal bitreg : registerfile := (others => (others => '0'));

begin
	
	out_a <=  bitreg(conv_integer(read_a));
	out_b <=  bitreg(conv_integer(read_b));
	
	writing:process(reset, clk, write)
	begin
		if (reset = '1') then
			bitreg(0) <= (others => '0');
			bitreg(1) <= (others => '0');
			bitreg(2) <= (others => '0');
			bitreg(3) <= (others => '0');
			bitreg(4) <= (others => '0');
			bitreg(5) <= (others => '0');
			bitreg(6) <= (others => '0');
			bitreg(7) <= (others => '0');
			bitreg(8) <= (others => '0');
			bitreg(9) <= (others => '0');
			bitreg(10) <= (others => '0');
			bitreg(11) <= (others => '0');
			bitreg(12) <= (others => '0');
			bitreg(13) <= (others => '0');
			bitreg(14) <= (others => '0');
			bitreg(15) <= (others => '0');
			bitreg(16) <= (others => '0');
			bitreg(17) <= (others => '0');
			bitreg(18) <= (others => '0');
			bitreg(19) <= (others => '0');
			bitreg(20) <= (others => '0');
			bitreg(21) <= (others => '0');
			bitreg(22) <= (others => '0');
			bitreg(23) <= (others => '0');
			bitreg(24) <= (others => '0');
			bitreg(25) <= (others => '0');
			bitreg(26) <= (others => '0');
			bitreg(27) <= (others => '0');
			bitreg(28) <= (others => '0');
			bitreg(29) <= (others => '0');
			bitreg(30) <= (others => '0');
			bitreg(31) <= (others => '0');
		elsif(write ='1' and clk'event and clk='1') then
			bitreg(conv_integer(write_address)) <= din;
		end if;
	end process;
	
end unti;