--sign extension
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;

entity signextension_mux is
port(
	func : in std_logic_vector(1 downto 0);
	immediate : in std_logic_vector(15 downto 0);
	out_b_input : in std_logic_vector(31 downto 0);
	alu_src : in std_logic;
	muxout_aluin : out std_logic_vector(31 downto 0));
end signextension_mux;

architecture sign_extension of signextension_mux is
	signal sign_extension_output : std_logic_vector(31 downto 0);
begin

signextensionblock: process(immediate, func)
begin
	case func is
		when "00" =>
			sign_extension_output(15 downto 0) <= (others => '0');
			sign_extension_output(31 downto 16) <= immediate;
		when "01" =>
			sign_extension_output(15 downto 0) <= immediate;
			sign_extension_output(31 downto 16) <= (others => immediate(15));
		when "10" =>
			sign_extension_output(15 downto 0) <= immediate;
			sign_extension_output(31 downto 16) <= (others => immediate(15));
		when "11" =>
			sign_extension_output(15 downto 0) <= immediate;
			sign_extension_output(31 downto 16) <= (others => '0');
		when others =>
	end case;
end process signextensionblock;

mux: process(sign_extension_output, out_b_input, alu_src)
begin
	if (alu_src = '0') then
		muxout_aluin <= out_b_input;
	else
		muxout_aluin <= sign_extension_output;
	end if;
end process mux;

end sign_extension;