Functional Verification of Calculator Design II
This project focused on the functional verification of Calculator Design II, an extension of the original Calculator Design I. The new design significantly enhances the calculator’s processing capability by allowing multiple commands to be handled simultaneously. Unlike the first version, which allowed only one command per port at a time, this iteration enables up to four commands from each of the four ports, resulting in a theoretical maximum of 16 concurrent operations.
To accommodate this increased complexity, the design includes two internal arithmetic pipelines—one dedicated to addition and subtraction, and another for shift operations. Due to this architecture, commands may be executed out of order. To ensure proper command tracking and correct result correlation, a 2-bit tag system was implemented. This tag uniquely identifies each command and helps associate responses with their corresponding requests.
Technical Components and Implementation
Functional Verification Approach
To ensure the correctness of the Calculator Design II, we conducted a structured verification process using SystemVerilog. The verification environment included several key components:
- Stimulus Generator (calc_gen) - Generates random calculator transactions, ensuring diverse test coverage. Transactions are controlled by a maximum count, and the generator tracks ongoing transactions.
- Interface (calc_if) - Defines the modports, ensuring proper signal directionality between different testbench components and the Device Under Test (DUT).
- Monitor (calc_monitor) - Concurrently observes all ports, capturing transactions and forwarding them to the scoreboard for analysis.
- Scoreboard (calc_scoreboard) - Compares expected results with actual DUT outputs. Mailboxes from both the master and monitor provide a mechanism for transaction validation.
- Transaction Model (calc_trans) - Assigns unique IDs to transactions and ensures randomization constraints are applied.
- Master (calc_master) - Fetches transactions from the generator, sends them to the DUT, and forwards them to the scoreboard for verification.
Results and Observations
During the verification process, the following functional bugs were identified:
- Shift Left Bug: Shift Left (SHL) operations on ports 0 and 1 produced faulty results that did not match expected outputs.
- Addition Inaccuracy: Initially, ADD operations did not execute correctly. Performance improved as test cycles progressed.
- Subtraction Performance Degradation: As the number of transactions increased, subtraction operations showed a decline in performance.
Functional Coverage Analysis
To ensure comprehensive testing, coverage models were implemented:
- Inputs and outputs were divided into three functional bins to analyze coverage.
- Response signals (‘01’ for success, ‘10’ for overflow, and ‘00’ for no response) were assessed to validate correctness.
Conclusion
This project provided valuable insight into the complexities of verifying a pipelined hardware design. By leveraging SystemVerilog-based verification methodologies, we successfully identified and documented key operational issues, ensuring the reliability of Calculator Design II. The structured testbench framework—comprising stimulus generation, transaction monitoring, and result validation—proved essential in detecting functional errors and verifying correct design behavior.
Through this project, we demonstrated the importance of rigorous verification in hardware design, ensuring correctness, efficiency, and robustness in digital arithmetic operations.