Introduction
This project focuses on the design and integration of a MIPS-based control unit using various hardware components.
The objective is to develop a fully functional datapath that interconnects all essential elements of a CPU, including control logic, memory units, and processing elements.
System Overview
The CPU is designed to execute MIPS assembly instructions, supporting fundamental operations such as arithmetic, logical operations, and memory access. The system consists of the following components:
- Next Address Unit: Determines the next instruction address.
- Opcode Route: Decodes instructions and generates control signals.
- PC & Instruction Cache: Maintains the program counter and stores instructions.
- Register File: Handles CPU registers and data storage.
- Sign Extension & MUX: Processes immediate values for ALU operations.
- ALU: Performs arithmetic and logical operations.
- Data Cache: Stores processed data and interacts with the ALU.
